Non-volatile memory (NVM) systems include arrays of NVM cells that are programmed using program bias voltages applied to program nodes. NVM systems can also be embedded within other integrated circuits, such as for example, microcontrollers and/or microprocessors. Many NVM systems, including embedded NVM systems, utilize smart program biasing and erase biasing where program/erase bias voltages are ramped, stepped and/or pulsed from a low voltage bias level to a higher voltage bias level in order to minimize stress to cells within the NVM array.
FIG. 1 (Prior Art) is a block diagram of an embodiment 100 for a non-volatile memory (NVM) system including a non-volatile memory 101 controlled by a memory management unit 120. The non-volatile memory 101 includes cell access logic circuitry 112, program voltage generation circuitry 102, and an NVM cell array 106. The NVM cell array 106 includes eight sectors (e.g., SECTOR0, SECTOR1. . . SECTOR7) of split-gate thin film storage (SGTFS) NVM cells, which include control gates, select gates, sources, and drains The memory management unit 120 includes an address register 122 that provides an address (ADDR) 128 to the cell access logic circuitry 101 that is used to select the cells to be accessed and programmed with the NVM cell array 106. The memory management unit 120 also includes a program data register 124 that provides the program data (PDATA) 130 that is used to program the cells selected for programming. Further, the memory management unit 120 includes control block 105 that is configured to control programming operations for the NVM system. During operation, the address 128 selects cells to be programmed within one of the sectors for the NVM cell array 106. As one example embodiment, the NVM cell array 106 can include a plurality of rows of cells; each row can have 144 cells (i.e., 144 bits), and the program data 130 can be 144 bits with zero values representing cells to be programmed and one values representing cells not to be programmed.
Within the NVM cell array 106, each sector further includes a control gate driver (CGDrv) and a source gate driver (SRCDrv). Each control gate driver (CGDrv) applies a high voltage (HV) output signal from the program voltage generation circuitry 102 to cells within the sector that have been selected for programming. A distribution line 108 feeds the HV output signal to control gate drivers. Each source gate driver (SRCDrv) applies a medium voltage (MV) output signal (VPRG) from the program voltage generation circuitry 102 to cells within the sector that have been selected for programming. A distribution line 110 feeds the MV output signal (VPRG) to the source gate drivers. As the source gate nodes are relatively low impedance nodes, a high current will travel along the distribution line 110. Due to the different distances and potentially long distance 104 (e.g., 2.2 millimeters) that this current will travel along distribution line 110, for example to SECTOR7, different and potentially large IR (current-resistance) voltage drops will occur. As such, the voltages actually applied to the NVM cells through the source drivers can be less than the desired program voltage level. For example, a MV output signal (VPRG) generated and output by the program voltage generator circuitry 102 at 6.0 volts may drop by 0.2 volts to 5.8 volts by the time it reaches SECTOR7 at the end of the distribution line 110. This voltage drop will be dependent upon the number of cells being programmed and the length along distribution line 110 that the programming currents will travel. As the control gate nodes are relatively high impedance nodes, the IR voltage drop along the distribution line 108 is not significant.
FIG. 2 (Prior Art) is a voltage level diagram 200 for representative variations in program pulse voltages due to IR voltage losses experienced in distributing program voltages to source drivers within an NVM array. The x-axis 204 represents time, and the y-axis 202 represents pulse voltage. For the embodiment 200, three program pulses are shown. Pulse voltage levels 206, 208, and 210 represent desired pulse voltage levels for pulses that ramp to 4.0 volts, 5.0 volts, and 6.0 volts, respectively. Actual voltage pulses 212, 214, and 216 do not reach the desired voltage levels due to IR voltage losses. For example, an IR voltage loss of about 0.1 volts can be experienced when the MV output signal (VPRG) of FIG. 1 is used to drive source nodes for 72 cells at 1 milli-Amp (mA) through program voltage drivers located at the end of a voltage distribution line that is 2.2 millimeters (mm). It is noted that the sheet resistance for the distribution line, the sector selected, and the current level will affect this IR loss. It is also noted that the current level is determined by the number of cells selected for programming within the NVM array.